Wafer-level integration of self-aligned high aspect ratio silicon 3D structures using the MACE method with Au, Pd, Pt, Cu, and Ir

• Mathias Franz,
• Romy Junghans,
• Paul Schmitt,
• Adriana Szeghalmi and
• Stefan E. Schulz

Beilstein J. Nanotechnol. 2020, 11, 1439–1449, doi:10.3762/bjnano.11.128

• Abstract The wafer-level integration of high aspect ratio silicon nanostructures is an essential part of the fabrication of nanodevices. Metal-assisted chemical etching (MACE) is a promising low-cost and high-volume technique for the generation of vertically aligned silicon nanowires. Noble metal

• with a reflectance below 0.3%. The demonstrated technology can be integrated into common fabrication processes for microelectromechanical systems. Keywords: black silicon; bottom-up; metal-assisted chemical etching (MACE); nanowires; wafer-level integration; Introduction Silicon nanostructures

• layer deposition (ALD), one can assume that a wafer-level integration is feasible. Figure 2 shows the surface of a silicon die after 90 cycles of Ir ALD. In this deposition phase, small Ir particles are grown. The particles agglomerate and start to form a continuous film. However, there are still voids